Practical method for determining inductances in deep submicron integrated circuits
Lead Inventors: Kenneth Shepard, Ph.D.Problem or Unmet Need:In circuit design the ability to accurately simulate and predict performance is a critical time and cost saving tool for the designer. Conventional design and simulation tools tend to ignore the role of interconnects in device performance. As the density of these interconnects increases and input signal frequencies climb ever higher, inductive coupling of interconnects can introduce significant timing error and noise to the signal. Determining the effect of interconnects is imperative for the design and layout of high frequency sub-micron ICs, and thus new models that incorporate this are needed. The invention is a model, which accounts for the inductive contribution of signal and power/ground interconnects to the noise and time delay in high frequency ICs. Few design tools currently account for this effect, and those methods that exist for doing so result in an overly complex and cumbersome matrix of inductance values. This model employs geometric rules of decomposition to decouple power-ground from signal carrying lines. This results in a simplified sparse matrix of inductance values where insignificant coupling interactions are ignored, while overall accuracy of the model is preserved.
Computes inductance values of interconnects and determines their effect on IC performance Sparse matrix is more efficient as well as accurate than existing techniques Inductance of long interconnects is accurately predicted
Extracting interconnect inductance values and their effect on performance during high frequency IC simulation
The invention is a model, which accounts for the inductive contribution of signal and power/ground interconnects to the noise and time delay in high frequency ICs. Few design tools currently account for this effect, and those methods that exist...
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