Kernel-Based Fast Aerial Image Computation For A Large Scale Design Of Integrated Circuit Patterns
A Method Of Simulating Aerial Images Of Large Mask Areas Obtained During The Exposure Step Of A Photo-Lithographic Process When Fabricating A Semiconductor Integrated Circuit Silicon Wafer Is Described. The Method Includes The Steps Of Defining Mask Patterns To Be Projected By The Exposure System To Create Images Of The Mask Patterns; Determining An Appropriate Sampling Range And Sampling Interval; Generating A Characteristic Matrix Describing The Exposure System; Inverting The Matrix To Obtain Eigenvalues As Well As The Eigenvectors (Or Kernels) Representing The Decomposition Of The Exposure System; Convolving The Mask Patterns With These Eigenvectors; And Weighing The Resulting Convolution By The Eigenvalues To Form The Aerial Images. The Method Is Characterized In That The Characteristic Matrix Is Precisely Defined By The Sampling Range And The Sampling Interval, Such That The Sampling Range Is The Shortest Possible And The Sampling Interval, The Largest Possible, Without Sacrificing Accuracy. The Method Of Generating Aerial Images Of Patterns Having Large Mask Areas Provides A Speed Improvement Of Several Orders Of Magnitude Over Conventional Approaches.
Patent Number: US6223139B1
Application Number: US1998153842A
Inventor: Wong, Alfred K. | Ferguson, Richard A.
Priority Date: 15 Sep 1998
Priority Number: US6223139B1
Application Date: 15 Sep 1998
Publication Date: 24 Apr 2001
IPC Current: G03F000720
US Class: 703005 | 356401 | 416021 | 703002
Assignee Applicant: International Business Machines Corporationmonk
Title: Kernel-based fast aerial image computation for a large scale design of integrated circuit patterns
Usefulness: Kernel-based fast aerial image computation for a large scale design of integrated circuit patterns
Summary: For simulating aerial images of large mask areas during fabrication of large scale semiconductor integrated circuit.
Novelty: Aerial images simulation for semiconductor IC silicon wafer fabrication, involves adding weighted convolutions of mask patterns to generate final set of aerial images of pattern replicated to form IC silicon wafer
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