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Zero-Delay Wakeup for Power-Gated Circuits
Detailed Technology Description
A new “zero-delay” latency hiding wakeup technique for power gated asynchronous circuits was developed that leverages the robustness of asynchronous circuits to delays and supply voltage variations, and can be used with any of the existing power gating schemes.
Others
Issued US patent 9,531,194
Ortega, C.; Tse, J.; Manohar, R.; "Static Power Reduction Techniques for Asynchronous Circuits," 2010 IEEE Symposium on Asynchronous Circuits and Systems (ASYNC), May, 2010
Country/Region
USA
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