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Methods and Systems for Decoding Polar Codes

詳細技術說明

Researchers from UC San Diego and McGill University in Canada have developed a new decoder technology that improves the performance of decoders for polar codes. The decoder architecture of this invention can be adjusted to reduce cost (e.g. smaller die area) and speed (e.g. through latency, number of cycles, number of elements etc). Details of this technology are published in US Patent Application (US 13/671,617 Methods and Systems for Decoding Polar Codes ).

*Abstract

Background: Communications and information technologies have fundamentally changed how we access information, interact as a society, and communicate. Today, wireless technology is everywhere in our daily lives and the ubiquitous nature of computing devices, cloud based storage, and the enhanced speed performance of the Internet mean that increasing our lives exploits remote stores of data.

Typically, to make communication reliable in the presence of noise, redundancy in the data is added before transmission as the intended receiver only has access to a noisy version of the data. However, if the redundancy is added through coding then it is possible to reconstruct the original data at the receiver in the presence of noise, which results in incorrect data being received through decision making processes at the receiver. Coding is therefore a central and essential element in any communication systems. However, adding this redundancy comes at the cost of reducing the effective rate of data transmission,

Designing capacity-achieving codes with an explicit construction eluded researchers until polar codes were developed. However, while demonstrating this benefit, polar codes required large code lengths to approach the capacity of the underlying channel. Despite these large code lengths, polar codes have two desirable properties for hardware implementation: 1) they explicitly describe in a recursive framework; and 2) do not require any kind of randomness to achieve good error correcting performance. It would be beneficial to address architectures and decoding processes that reduce the complexity of the processing elements thereby allowing the die footprint of any implemented hardware circuit to be reduced. 

*IP Issue Date

Nov 3, 2015

*Principal Investigation

Name: Warren Gross

Department:

Name: Camille Leroux

Department:

Name: Ido Tal

Department:

Name: Alexander Vardy

Department:

Name: Alexander Raymond

Department:

Name: Gabi Sarkis

Department:

申請號碼

9176927

其他

Tech ID/UC Case

22034/2011-127-0

Related Cases

2011-127-0

國家/地區

美國