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HDRL: Homogeneous Dual-Rail Logic For DPA Attack Resistive Secure Circuit Design

技術應用: HDRL is applicable to any standard cell-based crypto-LSI that deals with personal information. Possible applications include smart cards, mobile devices, SIM cards, and health monitoring devices. When one designs LSIs for such applications, the designer is able to achieve high DPA (Differential Power Analysis) attack resistivity using HDRL.

詳細技術說明: Differential Power Analysis (DPA) side-channel attacks pose serious threats for embedded system security. Wave Dynamic Differential Logic (WDDL) was proposed as a countermeasure that can be incorporated into a conventional ASIC design flow using standard cells. However, simulations show that DPA attacks on WDDL still leak secret keys to adversaries. To respond to this critical industry need, UCI researchers have created Homogeneous Dual-Rail Logic (HDRL), a standard cell level DPA attack countermeasure that theoretically guarantees fully balanced power consumption and significantly improves the DPA attack resistivity of hardware. Experimental results on the AES S-Box circuit show that HDRL successfully prevent DPA attacks in all cases. In addition, HDRL achieves such higher security with only 100.0% energy overhead while WDDL incurs 231.7% energy overhead. Also, HDRL requires the same area overhead as WDDL. HDRL’s better resistivity and lower energy overhead make it a promising countermeasure for standard cell based crypto-applications.

*Abstract: HDRL (Homogeneous Dual-Rail Logic) is a standard cell level DPA (Differential Power Analysis) attack countermeasure that theoretically guarantees fully-balanced power consumption and has been shown to significantly improve the DPA attack resistivity of hardware with low energy overhead and no delay overhead over conventional countermeasures.

*Principal Investigation: Name: Nikil Dutt
Department:

Name: Kazuyuki Tanimura
Department:

附加資料: Patent Number: US8395408B2
Application Number: US13286136A
Inventor: Tanimura, Kazuyuki | Dutt, Nikil
Priority Date: 29 Oct 2010
Priority Number: US8395408B2
Application Date: 31 Oct 2011
Publication Date: 12 Mar 2013
IPC Current: H03K001900
US Class: 326008 | 326009 | 326010
Assignee Applicant: The Regents of the University of California
Title: Homogeneous dual-rail logic for DPA attack resistive secure circuit design
Usefulness: Homogeneous dual-rail logic for DPA attack resistive secure circuit design
Summary: HDRL method for facilitating design of DPA side-channel attack resistant secure circuits utilized in an electronic device. Uses include but are not limited to a smart card device, mobile device, subscriber identification module (SIM) card device and a health monitoring device.
Novelty: Homogenous dual-rail logic method for facilitating design for differential power analysis side-channel attack resistant secure circuits utilized in e.g. electronic device, involves providing input to complimentary AND cell

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