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Variable-length, high-speed asynchronous decoder circuit

总结: Lead Inventors: Steven NowickMethod and system for an asynchronous decoder circuit that operates on data coded using a variable-length coding technique are described. The method and system comprises of an input buffer for receiving input data comprising coded, variable-length data words. An alignment circuit shifts input data by an amount responsive to a control input. A logic circuit coupled to the alignment circuit decodes the coded, variable-length data words. Logic circuit and adder circuit are logically partitioned into multiple computational stages arranged in a computation thread. A completion circuit for produces a completion signal indicating the completion or incompletion of each computational stage.The method and system provides an improved Huffman decoder design that gives a higher ratio of performance to circuit area than is possible with existing circuit designs.

详细技术说明: Method and system for an asynchronous decoder circuit that operates on data coded using a variable-length coding technique are described. The method and system comprises of an input buffer for receiving input data comprising coded, variable-len...

*Inquiry: Calvin Chu Columbia Technology Ventures Tel: (212) 854-8444 Email: TechTransfer@columbia.edu

*Web Links: Patent number: WO0016486USPTO_1: US 6,865,668USPTO_2: US 6,408,421

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