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Novel Processing Method for Group III-V Semiconductor Surfaces

技術優勢

Extremely high capacitance density Reduces high leakage currents Low defect densities

技術應用

Semiconductors Transistors

詳細技術說明

Researchers at UC Santa Barbara have developed a processing method for group III-V semiconductor surfaces prior to high-dielectric constant dielectric deposition by atomic layer deposition (ALD) or another deposition method. The method exposes the III-V surface to alternating or repeated cycles of a remote or direct plasma, which may be a plasma of nitrogen or hydrogen or another gas, or a mixture of such gases, and a titanium precursor. This provides the low defect densities and extremely high capacitance densities without reaching limitations posed by high leakage currents.

*Abstract

A processing method for group III-V semiconductor surfaces prior to high-dielectric constant dielectric deposition by atomic layer deposition (ALD) or another deposition method. 

*IP Issue Date

Nov 17, 2015

*Principal Investigation

Name: Varistha Chobpattana

Department:

Name: Susanne Stemmer

Department:

申請號碼

9190266

其他

Background

Complementary metal-oxide-semiconductor (CMOS) is a technology for developing integrated semiconductors and transistors that amplify or switch electrical signals. CMOS transistors have been using silicon channels that limit capacitance density and induce high-voltage leaks. Group III-V compounds are semiconducting materials that feature higher carrier mobilities, increased capacitance density, and less voltage leakage than silicon channels.

Tech ID/UC Case

24867/2014-816-0

Related Cases

2014-816-0

國家/地區

美國