Compact Double Gated SRAM
- 詳細技術說明
- A highly dense form of a static random-access memory that takes advantage of gates on either side of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration.
- *Abstract
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A highly dense form of a static random-access memory that takes advantage of gates on either side of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts, and dense interconnection of 3D. The technology is compatible with CMOS and integration with digital logic, and provides high density improvements that will occur as devices move to sub-50 nm range. Cornell's design uses a thin silicon film that can conduct from the top as well as the bottom surface, allowing the partitioning of the cell for much higher densities than currently possible. The most important technology element of Cornell's approach to 3D integrated circuits is the ability to assemble planes of planar-connected devices and to interconnect them in the third direction to form the 3D layered structure. At the 100 nm technology level, with minimum-sizing criterion, one configuration obtains a 47% reduction versus bulk in cell size with static noise margins of 224 mV which is better than SOI at a similar cell ratio, a 42% reduction in cell delay versus bulk, and a standby current level between that of a bulk and SOI cell.
- *Licensing
- Patrick Govangpjg26@cornell.edu(607) 254-2330
- 其他
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Patent: 7,365,398
- 國家/地區
- 美國
