Media.Player

A Methodology for the Design of High-Performance Communication Architectures for System-On-Chips Using Communication Architecture Tuners

技術應用

This invention should find ready application in the realization of high performance system-on-chip communication architectures.

詳細技術說明

This invention is a general methodology for the design of custom system-on-chip communication architectures, which are flexible and capable of adapting to the varying communications needs of system components. The disclosed technique can be used to optimize any underlying communication-architecture topology by rendering it capable of adapting to the changing communication needs of the components connected to it. For example, more critical data may be handled differently, leading to lower communication latencies. This results in significant improvement in quality of service (QoS) metrics, including the overall system performance, observed communication bandwidth and bus utilization, and the system's ability to meet critical deadlines. The present technique is based on the addition of a layer of circuitry, called the communication architecture tuner (CAT), to each component. The CAT monitors and analyzes the internal state of, and communication transactions generated by, a system component and "predicts" the relative importance of communication transactions in terms of their impact of different system-level performance metrics. The results of the analysis are used by the CAT to configure the parameters of the underlying communication architecture to best suit the component's changing communication needs.

*Abstract

None

*IP Issue Date

Dec 20, 2005

*Principal Investigation

Name: Sujit Dey

Department:

Name: Kanishka Lahiri

Department:

Name: Ganesh Lakshminarayana

Department:

Name: Anand Raghunathan

Department:

附加資料

Patent Number: US6978425B1
Application Number: US2000576956A
Inventor: Raghunathan, Anand | Lakshminarayana, Ganesh | Lahiri, Kanishka | Dey, Sujit
Priority Date: 3 Mar 2000
Priority Number: US6978425B1
Application Date: 24 May 2000
Publication Date: 20 Dec 2005
IPC Current: G06F0009455 | G06F001750
US Class: 716105 | 716001 | 703023 | 703027 | 716108 | 716138 | 716002 | 716003 | 716004 | 716005 | 716006 | 716007
Assignee Applicant: NEC Corporation,Tokyo | The Regents of the University of California
Title: Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners
Usefulness: Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners
Novelty: Electronic system has interconnected components, at least one of which has communication architecture tuner that potentiates adaptation of electronic system for communication demand

主要類別

信息和通信技術/電信

細分類別

電信

申請號碼

6978425

其他

Intellectual Property Info

The invention is patent pending with non-exclusive license rights available.

Tech ID/UC Case

21108/2001-097-0

Related Cases

2001-097-0

國家/地區

美國