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Resonant clock distribution for very large scale integrated circuits

總結: Lead Inventors: Kenneth ShepardDescription: Method and system for distributing a high frequency clock with improved power efficiency skew and jitter performance is described. A circuit for distributing a clock signal in an integrated circuit including a capacitive clock distribution circuit having a conductor is described.A method and system for determining the capacitance of the clock distribution conductor and the circuitry is disclosed. The inductance value required to form a resonance circuit with the clock distribution conductor is determined. The resonance frequency is equal to the clock frequency. A parallel-connected inductor is coupled to the clock distribution conductor to provide inductance.The system and method provide a clock distribution circuit which offers lower power consumption improving the skew and jitter performance. It provides an integrated circuit clock distribution topology which enables efficient distribution of high speed clock signals in large and very large scale integrated circuits

詳細技術說明: Description: Method and system for distributing a high frequency clock with improved power efficiency skew and jitter performance is described. A circuit for distributing a clock signal in an integrated circuit including a capacitive clock distributi...

*Inquiry: Jim Aloise Columbia Technology Ventures Tel: (212) 854-8444 Email: TechTransfer@columbia.edu

*Web Links: Patent number: US20050057286USPTO_1: US 7,145,408USPTO_2: US 7,015,765

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