A High-Throughput Asynchronous Pipeline Style Using a Transition-Signaling Protocol
- 總結
- Steven M. Nowick, Ph.D.
- 技術優勢
- Reduces overhead communication of a high-speed synchronous clockAllows design of very high-throughput fine-grain pipeline circuits to the maximum extentAvoids explicit latches with a clocked-CMOS style to improve area and performanceUses simple, easily met, one-sided timing constraints for practical design that is easy to implementReduces pipeline cycle timePatent information:Patent Pending (WO/2002/035346)Tech Ventures Reference: IR M01-020
- 技術應用
- Wearable electronics such as watches, glasses, wristbands and athletic gearBiosensors with electronic interfacesTablet, laptop, computer microprocessorsLab on a chip technologyEthernet switch chipsLow-latency finite-impulse response filter chips
- 詳細技術說明
- Steven M. Nowick, Ph.D.
- *Abstract
-
None
- *Inquiry
- Jay HickeyColumbia Technology VenturesTel: (212) 854-8444Email: TechTransfer@columbia.edu
- *IR
- M01-020
- *Principal Investigation
-
- *Publications
- Montek, S., Nowick, S.M. “MOUSETRAP: High-speed Transition-signaling Asynchronous Pipelines” IEEE Transitions on VLSI. 2007 June; 15(6):684-698.
- *Web Links
- Patent number: US20040046590
- 國家/地區
- 美國
欲了解更多信息，請點擊 這裡
