Power Efficient, High Bandwidth Chip-to-Chip Signaling Using Fixed Load Encoding
- 詳細技術說明
- None
- *Abstract
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We present a new signaling system for high speed, short haul (1cm-1m), digital communications links that is applicable to printed circuit board, computer backplane and point-to-point applications operating at multi-gigabit data rates. This new design is a significant improvement over current differential signaling standards. This system substantially expands the information carrying capacity of these links while retaining the advantages of lower power-supply noise, fast current steering drivers, constant load and common mode noise rejection that characterizes differential links. It is possible to design links that use 30% to 40% less chip area and electrical power when compared to an equivalent differential link.
- *Principal Investigation
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Name: Donald Chiarulli, Professor
Department: Electrical and Computer Engineering
Name: Steven Levitan, Professor
Department: Electrical and Computer Engineering
- 國家/地區
- 美國
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