Activity Driven Adaptive Gating of Clock Tree (Bar Ilan)
Market demand for low power mobile computing and consumer electronics products has refocused VLSI design in the last decade on lowering power and energy efficiency. Many design methodologies and techniques have been developed, of which clock gating is most popular and well established in the design community. Clock gating is employed in all levels: system architecture, block design and local circuits. Once clock signal is applied to a functional block, the sequential elements and the clock-tree network consume around 50% of the dynamic power.This method deals with how to maximize the clock gating at block and circuit levels and can be used for any digital VLSI design. It uses a systematic, optimal algorithm to implement clock gating compared to intuitive ad-hoc methods used today.
Patent pending
Reduction of 15% in consumed power has been proved in real design flows.
We Believe reduction of consumed power can be further improved to 30% reduction.
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