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Rectangular Contact Lithography For Circuit Performance Improvement And Manufacture Cost Reduction

總結

An Optical Lithography Method Is Disclosed That Uses Double Exposure Of A Reusable Template Mask And A Trim Mask To Fabricate Regularly-Placed Rectangular Contacts In Standard Cells Of Application-Specific Integrated Circuits (Asics). A First Exposure Of The Reusable Template Mask With Periodic Patterns Forms Periodic Dark Lines On A Wafer And A Second Exposure Of An Application-Specific Trim Mask Remove The Unwanted Part Of The Dark Lines And The Small Cuts Of The Dark Lines Left Form The Rectangular Regularly-Placed Contacts. All Contacts Are Placed Regularly In One Direction While Unrestrictedly In The Perpendicular Direction. The Regular Placement Of Patterns On The Template Mask Enable More Effective Use Of Resolution Enhancement Technologies, Which In Turn Allows A Decrease In Manufacturing Cost And The Minimum Contact Size And Pitch.; Since There Is No Extra Application-Specific Mask Needed Comparing With The Conventional Lithography Method For Unrestrictedly-Placed Contacts, The Extra Cost Is Kept To The Lowest. The Method Of The Invention Can Be Used In The Fabrication Of Standard Cells In Application-Specific Integrated Circuits (Asics) To Improve Circuit Performance And Decrease Circuit Area And Manufacturing Cost.

附加資料

Patent Number: US7569308B2
Application Number: US200565413A
Inventor: Wang, Jun | Wong, Alfred K. | Lam, Edmund Y.
Priority Date: 24 Feb 2004
Priority Number: US7569308B2
Application Date: 24 Feb 2005
Publication Date: 4 Aug 2009
IPC Current: G03F000900 | G03F000114 | G03F000720 | H01L002100
US Class: 430005 | 430311 | 430322 | 430394
Assignee Applicant: The University of Hong Kong
Title: Rectangular contact lithography for circuit performance improvement and manufacture cost reduction
Usefulness: Rectangular contact lithography for circuit performance improvement and manufacture cost reduction
Summary: For fabricating regularly placed rectangular contacts in standard cells of application specific integrated circuit (ASIC).
Novelty: Optical lithography method for fabrication of rectangular contacts in standard cells of application specific integrated circuit, involves performing double exposure of reusable mask and specific trim mask with respect to wafer

主要類別

電子

細分類別

電路設計

申請號碼

US200565413A

國家/地區

香港