Deep-Learning Accelerator And Analog Neuromorphic Computation With CMOS-Compatible Charge-Trap-Transistor (CTT) Technique

High Speed  Low power consumption  Compatible with existing commercial manufacture processes  Low design costs

Deep neural networks accelerator Image/voice recognition Artificial intelligence

UCLA researchers from the Department of Electrical Engineering have developed a charge trap transistor-based computing architecture for neural networks applications. This design increases the computing speed and cuts down the power consumption. Additionally, it is compatible with existing commercial processors. The inventors designed a CTT with high-k-metal-gate (HKMG) memory-based non-volatile memory (eNVM) solution to increase computation speed and energy efficiency in deep-learning accelerator applications. Since certain information stored on-chip in a convolutional neuron network (CNN) is repeatedly read and used during computation, the fast reading and slow writing characteristics of CTT-based eNVM fit perfectly into a CNN accelerator. Additionally, using the CTT-based eNVM in deep learning hardware architecture does not require new manufacturing materials or processes, making them perfectly compatible with existing CMOS chips. Therefore, they could easily be commercially implemented for high performance and low power computing in artificial intelligence applications.

Background

Deep neural networks have wide applications in industries such as machine vision, voice recognition and artificial intelligence- all of which are billion dollar markets growing rapidly each year. Current commercial computing processors (such as CPU, GPU and accelerators) can hardly keep up with the increase in computation demand for complex deep neural network algorithms. The design limits in energy efficiency and on-chip memory density hinders the expansion of computation capabilities in existing commercial processors.

In recent years, analog computing engines have shown promises in increasing computing speed and energy efficiency, as well as decreasing design costs. However, these devices require new material and additional manufacturing processes that are not supported by major CMOS foundries. Hence, they are incompatible with existing commercial CMOS chips.

Additional Technologies by these Inventors

• Self-synchronized RF Interconnect for 3-dimensional Circuit Integration
• Submillimeter-wave Signal Generation by Linear Superimposition of Phase-shifted Fundamental Tone Signals
• Digital Regenerative Receiver for Millimeter-Wave and Sub-Millimeter-Wave Imaging and Communication
• Phase Coherent Frequency Divider
• Off-Chip Multi-Band RF-Interconnect (OMRF-I) Transceiver for Future Advanced High Speed Memory Interface
• Origamic Topology for Analog and Mixed-Signal Circuit Applications
• Digital Oscillator Method to Implement Non-Contact Sensors for Gesture Detection Displays
• Interference Tolerant Radar System for Self-Driving Vehicles
• Grouping Algorithm For Touchscreen Finger Position Detection
• On-Chip Tunable Artificial Dielectrics
• Interleaved 3D On-Chip Differential Inductor And Transformer
• Sub-Carrier Successive-Approximation Mm-Wave Radar For High-Resolution 3D Imaging
• Millimeter-Wave CMOS Transceiver with PCB Antenna for Contactless Wave-Connectors
• Hollow Plastic Waveguide ("Wave Cable") Based High Speed And Low Power Data Center Inter-Server Link
• Metal-Coated Flexible Dielectric Waveguides For Millimeter-Wave Multi-Lane Wireline Communication
• An Efficient Architecture To Compute Sparse Neural Network

Tech ID/UC Case

29381/2018-003-0

Related Cases

2018-003-0

美国

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