Differential Power Analysis Resistant Logic Style
1. The modification is a technically feasible and systematic modification to what is currently available; and, 2. The approach is flexible to accommodate any silencing gene candidates.
Smart cards Any security application that is relying on standard CMOS technology or FPGA design flow.
A novel logic style is developed in which every logic gate consumes constant power independent of the input signal. It is called Wave Dynamic Differential Logic (WDDL) and is DPA resistant. Moreover, a routing scheme is developed that provides constant load capacitance for true and false outputs of the WDDL gates which results in constant power cost. Using these innovations, a design methodology that is suitable for integration in a common automated standard cell ASIC or FPGA design flow is developed.
Patent Number: US7924057B2
Application Number: US2003586846A
Inventor: Verbauwhede, Ingrid | Tiri, Kris J. V.
Priority Date: 13 Feb 2004
Priority Number: US7924057B2
Application Date: 20 Jul 2006
Publication Date: 12 Apr 2011
IPC Current: H03K001900 | G06F000700 | G06F001750 | H03K001920
US Class: 326093 | 326104 | 327200 | 716014
Assignee Applicant: The Regents of the University of California
Title: Logic system for DPA resistance and/or side channel attack resistance
Usefulness: Logic system for DPA resistance and/or side channel attack resistance
Summary: Used in subscriber identity module (SIM) card in global system for mobile communication (GSM) mobile phone, electronic wallet, automatic teller machine (ATM) card, credit card, pay television (TV) and secure identification (ID) card containing biometric information.
Novelty: Simple dynamic differential logic in credit card, has pre-discharge stage that provides evaluation phase for passing differential information and pre-discharge phase for pre-discharging portion of differential logic cell
电子
计算机，通信和消费电子产品 /小工具
7924057
State of Development The complete design flow is developed that integrates usage of the WDDL gates and differential routing in the standard CMOS technology and FPGA design flow. About 128 WDDL library cells are designed. This design methodology is used to fabricate an embedded biometric authentication system (ThumbPod) using the 0.18m CMOS technology. The chip is tested against the DPA attack and it proved to provide resistance against differential power analysis side-channel attack. This case is also related to, [ LA 2003-442ABOUT THE LAB This and other developments in Embedded Security can be found at the UCLA Embedded Security Group in the Electrical Engineering Department of UCLA, http://www.emsec.ee.ucla.edu Background Security chips leak information through power consumption, timing, and electro-magnetic radiation although they are secure against mathematical attacks. One of the most effective side channel attacks to the encryption ICs is the differential power analysis attack. In DPA, the attacker measures the power consumption of the chip while it encrypts and by doing a statistical analysis he can extract the secret-key. This is due to the asymmetry of the power consumption in the standard CMOS logic gates since they have power characteristic that is dependent on the input signals. Different techniques have been proposed to prevent this information leakage: interleaved dummy instructions, random power consumption, duplicate logic, etc.; however, all of these methods have been circumvented. Additional Technologies by these Inventors Tech ID/UC Case 20209/2004-155-0 Related Cases 2004-155-0
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