Warp processor for dynamic translation of binaries to FPGA circuits
- 技术优势
- 1) The invention utilizes single pass optimizations that require less memory (up to 20 times less) and execution time than most current commercial approaches. 2) The technique offers reduced energy consumption (up to 74%) over corresponding embedded benchmarks. 3) Dynamic partitioning is completely transparent, allowing a designer to gain the benefits of partitioning, while writing a regular software application using standard software tools. 4) The warp processor’s dynamic partitioning can adapt to an application’s actual usage in real-time, eliminating the need for optimization via cumbersome static simulations.
- 技术应用
- UC’s invention has immense commercial applications as almost any kind of microprocessor-based technology can utilize the benefits of warp processing. These include everything from video and audio processing, encryption and decryption, encoding, compression and decompression and bioinformatics to mainframe computers and even relatively simple consumer electronic items such as TV’s. Embedded systems such as medical instruments and security scanners can also perform real-time recognition using warp-enhanced FPGA’s.
- 详细技术说明
- UC researchers have invented a warp processor, a microprocessor that allows the dynamic and transparent partitioning of an executing software’s binary kernels into customized FPGA circuits resulting in 2 to 100 times speed up over executing on microprocessors. The UC invention’s dynamic approach allows techniques associated with dynamic software optimization to be applied to hardware/software partitioning. The profiler, compiler and synthesis tools are entirely on-chip, so that warp processor partitioning does not require extra designer effort or disruption to standard tool flow.
- *Abstract
-
Traditional microprocessor software bits represent sequential instructions that are executed by a programmable microprocessor. In contrast, modern FPGA software bits are mapped onto FPGA’s configurable logic fabric via a circuit. Both software types free developers from needing to design hardware. A computation may execute faster on an FPGA than as sequential instructions on a microprocessor because a circuit allows concurrency (single rather than multiple cycle passes) from the bit to the process level
- *IP Issue Date
- Apr 8, 2008
- *Principal Investigation
-
Name: Roman Lysecky
Department:
Name: Greg Stitt
Department:
Name: Frank Vahid
Department:
- 附加资料
- Patent Number: US7356672B2
Application Number: US2004856062A
Inventor: Vahid, Frank | Lysecky, Roman Lev | Stitt, Gregory Michael
Priority Date: 28 May 2004
Priority Number: US7356672B2
Application Date: 28 May 2004
Publication Date: 8 Apr 2008
IPC Current: G06F001576 | G06F000738 | G06F000944
US Class: 712037 | 717159
Assignee Applicant: The Regents of the University of California
Title: Warp processor for dynamic hardware/software partitioning
Usefulness: Warp processor for dynamic hardware/software partitioning
Summary: For hardware/software partitioning in wrap processor.
Novelty: Hardware/software partitioning method, involves updating binary to access configuration logic other than critical code regions, when binary is executed in processor
- 主要类别
- 电子
- 细分类别
- 电脑系统
- 申请号码
- 7356672
- 其他
-
Other Information
UCR is looking for commercial partners who are interested in utilizing warp processing for their applications. For more information, please contact Dr. Eric Tonui (eric.tonui@ucr.edu) on 951 827 4967.
Additional Technologies by these Inventors
Tech ID/UC Case
19151/2004-390-1
Related Cases
2004-390-1
- 国家/地区
- 美国
