Accelerating flash memory performance by partial sensing (Technion)
Fast access time is a fundamental requirement while employing flash for system usage. As flash storage capacity doubles every two years, improvements in read speed are required to cope with the growing desired data transfer rates. Flash enhancements have been suggested, such as aggressive scaling, which positions NAND flash as currently the most dense semiconductor circuit, and other innovations for faster read and program (write) operations. In NAND flash, due to the nanometer-scale manufacturing process, memory cells are manufactured with different electrical parameters. Read operation is performed in groups of cells and read latency depends on cell parameters. As a result, the read operation and latency are determined by the worst cell in the memory array. The read operation is also used during program and erase operations as an integral part (cell verify). Consequently, accelerating the read operation by reducing read latency will induce data errors.The presented novel algorithm performs read operation with reduced latency, and uses a specially-designed error detection code that can detect any number of relevant errors. If read errors occur, Read is applied again with higher probability for success. As a result, the average read latency can be reduced. Simulations show 30% improvement. As Read is also part of Write and Erase operations, the NAND Flash Write, Read and Erase operations can all be accelerated. Implementation of this innovative scheme requires a small degree of data redundancy and hardware overhead, and does not require any changes in the core technology or fabrication process.
Simulations show 30% flash memory performance acceleration, compared to traditional performance
• Smartphones
• E-books and tablets
COM-1343
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