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Under-Bump Metallization Layers and Electroplated Solder Bumping Technology for Flip-Chip微細間距倒裝銲凸點電鍍製備技術

总结

Electroplating-based flip chip solder preparation process had been widely used over other preparation methods. Although it is cheaper and is able to achieve the material deposition on the fine pitch I/O pads, the solder bumps resulted are not uniform and not quality-guaranteed.

In this invention, manufacturing of fine-pitch solder bumps on the wafers is made possible. It can achieve solder bumps manufacturing with 50microns space. The solder bump size is from 50 to 300microns. The solder materials will not collapse on the surface of wafers during the reflow process because of a specially designed layer. Series of photolithography process including the designing method of related photolithography mask can achieve the high quality and thick photoresist. The parameters of electroplating process and the process designed are also provided to improve the quality of solder and eliminate the IMC effect.

技术优势

1. High quality and thick photoresist (50-175microns)
2. Improved quality of Cu and solder
3. Elimination of IMC effect
4. Photolithography process is improved
5. Lower cost

技术应用

- Solder bumping process
- Electronic product packaging application
- Wafer bumping production

附加资料

Patent Number: US7199036B2
Application Number: US2004854174A
Inventor: Chan, Chingho Philip | Xiao, Guowei David
Priority Date: 31 May 2003
Priority Number: US7199036B2
Application Date: 27 May 2004
Publication Date: 3 Apr 2007
IPC Current: H01L002144 | C25D000712 | H01L002160 | H01L002302 | H01L0023485
US Class: 438613 | 257E21508 | 257E23021
Assignee Applicant: The Hong Kong University of Science & Technology
Title: Under-bump metallization layers and electroplated solder bumping technology for flip-chip
Usefulness: Under-bump metallization layers and electroplated solder bumping technology for flip-chip
Summary: For forming solder bumps on wafer or substrate for flip chip attachment.
Novelty: Forming solder bumps for flip chip, by forming bump-reflow-control layer, forming desired pattern, and forming thick photoresist film with designed holes using hermetic part with special design and special photolithography process

主要类别

电子

细分类别

电路设计

申请日期

27 May 2004

申请号码

US 10/854174

专利信息

US 7199036

ID号码

TTC.PA.211S

国家/地区

香港