Three Dimensional Integrated Circuits
The invention is a simple method to fabricate multiple layers of transistors with one on top of each other in a 3D structure. Compare with some of the current practice, the new method is simple, flexible, controllable and capable to form much better performance transistors.
The use of Metal-Induced Lateral Crystallization with special pattern of Metal placement results in much better control of the grain location, thus the transistors can be precisely placed on a single grain. In such, transistors with single crystal performance can be formed on polysilicon film with precise control. It solves the problem of poor performance of transistors formed on polysilicon film.
Fabrication of transistors in 3D can lead to significant area saving and higher speed of operation, especially when compared with 2D technology. Unlike existing method to form 3D circuits, the new method provides flexibility to form not only 2 layers but also multiple layers. Also, the new invention does not require the use of special processing technology and is compatible with the current 2D technology.
The invention can potentially provide a technological breakthrough in the mainstream IC technology to form the next generation high density, high performance 3D integration circuits. Also, it allows high performance transistors to be fabricated on top of any micro structure (such as MEMS).
1. Simple and flexible way to fabricate transistors in a 3D manner
2. Area saving and higher speed of operation
3. Allow for multi-layers transistors
4. Allow for high performance transistors formed on polysilicon film
5. Compatible with current technology
6. Allow for fabricating high performance transistors on top of any micro structure (such as MEMS)
- Static RAM (SRAM)
- 3D Silicon-on-Insulator (SOI) CMOS
- Micro-electro-mechanical systems (MEMS)
Patent Number: US6727517B2
Application Number: US2001964530A
Inventor: Chan, Man Sun John | Chan, Philip C. H. | Chan, Wing Chung Victor
Priority Date: 28 Sep 2001
Priority Number: US6727517B2
Application Date: 28 Sep 2001
Publication Date: 27 Apr 2004
IPC Current: H01L002120 | H01L0021822 | H01L002706
US Class: 257066 | 257072 | 257075 | 257E21133 | 257E21614 | 257E27026 | 438166 | 438489 | 438660
Assignee Applicant: The Hong Kong University of Science & Technology
Title: Three dimensional integrated circuits
Usefulness: Three dimensional integrated circuits
Summary: For forming semiconductor crystals to fabricate electronic circuit such as integrated circuits (claimed) especially transistors, in microelectromechanical system (MEMS).
Novelty: Semiconductor crystals formation method for fabricating integrated circuits, involves annealing amorphous silicon film and subjecting it to metal induced lateral crystallization at specific temperature and time
电子
电路设计
28 Sep 2001
US 6727517
TTC.PA.140
香港
