Stencil Mask Design Method and Under Bump Metallurgy for C4 Solder Bump用於鉛/錫及無鉛焊料的小間距倒裝焊凸點模板印刷製備技術
A method for the fine-pitch stencil mask design for stencil printing bumping technology for eutectic Sn/Pb and lead-free solder material is described. In the method, a reflowing enhancement layer is introduced to improve the solder quality and reduce the pitch of solder bumps. The method of forming the layer is described as well as the forming method of matching under-bump metallurgy layer. The method of stencil mask design can match various sizes and pitch of the solder bumps. The designed mask is fixed on the stencil printer to deposit the solder materials with the required patterns. This method can increase the solder paste volume to increase the height of solder bumps after the reflowing process.
1. Higher reliability of solder bump
2. Available for various solder materials and lead-free
3. materials
4. Smaller pitch solder bumps
5. Improved quality of solder
6. Reduced number of metal layers
7. Low cost process for wafer bumping
- Wafer-level flip chip packaging technology
- Solder bumping process
- Electronic product packaging application
Patent Number: US7135355B2
Application Number: US2004859089A
Inventor: Chan, Chingho Philip | Xiao, Guowei David
Priority Date: 3 Jun 2003
Priority Number: US7135355B2
Application Date: 3 Jun 2004
Publication Date: 14 Nov 2006
IPC Current: H01L002144 | H01L002128 | H01L002148 | H01L002150 | H01L002160 | H01L0021768 | H01L0023485
US Class: 438113 | 257E21508 | 257E23021 | 438108
Assignee Applicant: The Hong Kong University of Science & Technology
Title: Stencil mask design method and under bump metallurgy for C4 solder bump
Usefulness: Stencil mask design method and under bump metallurgy for C4 solder bump
Summary: For forming solder bumps for a flip chip on a wafer or substrate with semiconductor devices.
Novelty: Formation of solder bumps for flip chip on wafer or substrate with semiconductor devices comprises depositing thin metal film comprising central under-bump metallurgy layer and reflowing enhancement layers
电子
半导体
3 Jun 2004
US 10/859089
US 7135355
TTC.PA.212S
香港
